1. Field of the Invention
The present invention generally relates to a multilayer board and a semiconductor device, and especially relates to a multilayer board and a semiconductor device wherein a grounding layer, a power supply layer, a signal layer, and a via that connects between the layers are prepared.
2. Description of the Related Art
FIGS. 1 through 5 show examples of the multilayer board and the semiconductor device of the conventional technology. FIG. 1 is an elevational view of an example of a semiconductor device 1 of the conventional technology, FIG. 2 is a sectional view expanding and showing a multilayer board 3 of the semiconductor device 1, and FIG. 3 is a bottom plan view of the multilayer board 3.
In the example shown in FIG. 1, the semiconductor device 1 is mounted on a system board 8. The semiconductor device 1 includes a semiconductor element 2 and the multilayer board 3. The semiconductor element 2 is mounted on the upper surface of the multilayer board 3 by flip-chip bonding, using a vamp 4.
Further, a land 6 is formed on the bottom surface of the multilayer board 3, and a connection pin 7 (solder ball), which serves as an external connection terminal, is installed at the land 6. The semiconductor element 2 is connected to the system board 8 through the multilayer board 3 by joining the connection pin 7 to a connection electrode 9.
As shown in FIG. 2, the multilayer board 3 includes a grounding layer 11, a signal layer 12, a power supply layer 13, and another grounding layer 14, which are sequentially formed in layers from the upper part of an insulation material 10. Each of the layers 11 through 14 is formed in the direction of the face of the multilayer board 3 (i.e., in the horizontal direction of FIG. 2).
Further, a grounding via 15, a signal via 16, and a power supply via 17 are formed in the insulation material 10. Each of the vias 15 through 17 is formed in the direction that is approximately perpendicular to the layers 11 through 14 (i.e., approximately in the vertical direction of FIG. 2.), such that predetermined connections of the layers 11 through 14 are carried out.
Specifically, the grounding via 15 connects the grounding layers 11 and 14 and a grounding land 6G. Further, a grounding pin 7G is provided to the grounding land 6G, and the grounding pin 7G is connected to a grounding electrode 9G of the system board 8. Similarly, the signal via 16 connects the signal layer 12 and a signal land 6S. Further, a signal pin 7S is provided to the signal land 6S, and the signal pin 7S is connected to a signal electrode 9S of the system board 8. Furthermore, the power supply via 17 connects the power supply layer 13 and a power supply land 6P. Further, a power supply pin 7P is provided to the power supply land 6P, and the power supply pin 7P is connected to a power supply electrode 9P of the system board 8.
In order to facilitate reading FIG. 2, a lattice pattern is given to grounding-related elements such as the grounding layers 11 and 14, the grounding via 15, the grounding land 6G, and the grounding pin 7G. Further, a dotted pattern is given to signal-related elements such as the signal layer 12, the signal via 16, the signal land 6S, and the signal pin 7S, and a slashed pattern (hatching) is given to power supply-related elements such as the power supply layer 13, the power supply via 17, the power supply land 6P, and the signal pin 7P. Further, the solder ball 7, when individually specified by different functions, is called the grounding pin 7G, the signal pin 7S, and the power supply pin 7P, as described above.
With reference to FIG. 3, the bottom of the multilayer board 3 (the bottom surface 18) is described. As shown in FIG. 3, in the conventional multilayer board 3, all of the three kinds of the pins, namely, the grounding pin 7G, the signal pin 7S, and the power supply pin 7P, are provided in the shape of a lattice on the bottom surface 18.
FIG. 4 shows a signal wiring line that connects the semiconductor element 2 and the signal pin 7S. Further, FIG. 5 shows a sectional view of FIG. 4 intersected by a plane represented by the line A—A.
The vamp 4 provided to the semiconductor element 2 is connected to a pad 19 formed on the upper surface of the multilayer board 3. The pad 19 is connected to the signal land 6S through the signal via 16A, the signal layer 12, and the signal via 16B. Here, a clearance 14A is formed in the grounding layer 14 so that the signal via 16B and the grounding layer 14 are not short-circuited. The signal via 16B passes through the clearance 14A, and is connected to the signal land 6S.
Around the signal via 16B, two or more grounding vias 15 are provided, as shown in FIG. 5. The grounding vias 15 are structured such that they are connected to the grounding layer 11 and the grounding layer 14. By structuring the multilayer board 3 in this manner, impedance of the signal via 16B is controlled, and degradation of signal characteristics is prevented. Details of the structure are indicated by the Provisional Publication H6-85099.
Conventionally, not much attention has been paid to the magnitude (diameter W2: indicated by an arrow W2 shown in FIG. 4) of the clearance 14, and the clearance has been simply set up at arbitrary dimensions so as to allow the signal via 16B to pass through. For this reason, the diameter W2 of the clearance 14A has been set up smaller than the diameter of the signal land 6S (indicated by an arrow W1 in FIG. 4), that is, W2<W1.
In recent years, the number of pins to be provided to the multilayer board 3 has been rapidly increasing. For example, in a 1000-pin multilayer board 3, 500 signal pins 7S, 250 power supply pins 7P, and 250 grounding pins 7G are provided. Further, demands are growing for a larger number of signal pins 7S without changing the size of the present multilayer board 3.
If a demand is that the number of the signal pins 7S of the 1000-pin multilayer board 3 is to be increased to 700 from 500, the numbers of the grounding pins 7G and the power supply pins 7P will have to be decreased to 150 pins, respectively. Consequently, capacity of the power supply and grounding becomes inadequate, causing problems such as voltage drops and simultaneous switching noise.
In order to solve the problems as above, a method is conceived whereby the numbers of the power supply layers and the grounding layers are increased, such that the power supply and grounding capacities are improved. However, this method results in an increase in manufacturing costs, an increase in the thickness of the multilayer board 3 and the like, due to the increased number of layers.
Further, at the external connection terminal portion of the bottom surface of the multilayer board 3, a large coupling factor, therefore, a large capacitance is present between the land 6 or the connection pin 7, and the wide layer (e.g., the grounding layer 14 in FIG. 4). For this reason, the impedance of this portion will become lower than the impedance of the signal via 16. Consequently, signal reflection arises at the bottom surface portion of the multilayer board 3, and degradation of the signal characteristics occurs. Therefore, impedance matching in this portion is required.
It is effective to provide a plurality of grounding vias 15A through 15C along the circumference of the signal via 16B (refer to FIG. 4 and FIG. 5), as indicated by the above mentioned Provisional Publication H6-85099, thereby the impedance of the signal via 16B is controlled. However, conventionally, the grounding vias 15A through 15C are simply provided around the perimeter of the signal via 16B, without paying attention as to an efficient manner of the arrangement.